1. Field of the Invention
The present invention relates to high speed latch comparators.
2. Background Art
Commercialization of the Internet has proven to be a mainspring for incentives to improve network technologies. Development programs have pursued various approaches including strategies to leverage use of the existing Public Switched Telephone Network and plans to expand use of wireless technologies for networking applications. Both of these approaches (and others) entail the conversion of data between analog and digital formats. Therefore, it is expected that analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) will continue to perform critical functions in many network applications.
Because ADCs find uses in a wide variety of applications, design of these circuits has evolved along many paths to yield several distinct architectures, including “delta sigma,” “successive approximation,” “pipelined,” and “flash.” Each architecture has its benefits and drawbacks. Paramount among these is a tradeoff between bandwidth and degree of resolution. FIG. 1 is a graph 100 that shows the tradeoff between bandwidth and degree of resolution for the various ADC architectures. Graph 100 comprises a “degree of resolution” axis 102 and a “bandwidth” axis 104. The relative positions of the different ADC architectures are plotted with respect to axes 102, 104: a “delta sigma” region 106, a “successive approximation” region 108, a “pipelined” region 110, and a “flash” region 112. In the design of network technologies, data conversion has often presented itself as a bottleneck that impedes the rate at which information is transmitted. Therefore, those ADC architectures that can support large bandwidths for rapid transfers of data have been favored for network applications.
FIG. 2A is a block diagram of an exemplary conventional two-bit flash ADC 200. ADC 200 comprises a first comparator “A” 202, a second comparator “B” 204, a third comparator “C” 206, a priority encoder 208, a first resistor “R1” 210, a second resistor “R2” 212, a third resistor “R3” 214, and a fourth resistor “R4” 216. Each of R1 210, R2 212, R3 214, and R4 216 has the same measure of resistance. R1 210, R2 212, R3 214, and R4 216 are connected in series between an analog ground “VAG” 218 and a supply voltage “V” 220. R1 210 is connected between VAG 218 and a first node “N1” 222. R2 212 is connected between N1 222 and a second node “N2” 224. R3 214 is connected between N2 224 and a third node “N3” 226. R4 216 is connected between N3 226 and V 220. In this configuration, the voltage at N1 222 is equal to V/4, the voltage at N2 224 is equal to V/2, and the voltage at N3 226 is equal to 3V/4.
The inverting terminals of comparators A 202, B 204, and C 206 are connected to, respectively, N1 222, N2 224, and N3 226. An analog signal “x” 228 is received at an input 230, which is connected to the noninverting terminals of comparators A 202, B 204, and C 206. A quantized signal is produced at the output terminal of each comparator. Quantized signals “w1” 232, “w2” 234, and “w3” 236 are produced at the output terminals of, respectively, comparators A 202, B 204, and C 206. Each quantized signal has a voltage with a value “LOW” or a value “HIGH” depending upon whether a corresponding value of the voltage of analog signal x 228 is less than (or equal to) or greater than the voltage at the inverting terminal of the corresponding comparator (i.e., the reference voltage of the comparator). For example, when the value of the voltage of analog signal x 228 is less than or equal to V/4, the values of the voltages of w3 236, w2 234, and w1 232 are equal to, respectively, LOW, LOW, and LOW. When the value of the voltage of analog signal x 228 is less than or equal to V/2, but greater than V/4, the values of the voltages of w3 236, w2 234, and w1 232 are equal to, respectively, LOW, LOW, and HIGH. When the value of the voltage of analog signal x 228 is less than or equal to 3V/4, but greater than V/2, the values of the voltages of w3 236, w2 234, and w1 232 are equal to, respectively, LOW, HIGH, and HIGH. When the value of the voltage of analog signal x 228 is less than or equal to V, but greater than 3V/4, the values of the voltages of w3 236, w2 234, and w1 232 are equal to, respectively, HIGH, HIGH, and HIGH. It is because quantized signals w1 232, w2 234, and w3 236 are produced simultaneously that two-bit flash ADC 200, also referred to as a “parallel-comparator” ADC, is capable of supporting large bandwidths for rapid transfers of data.
The output terminals of comparators A 202, B 204, and C 206 are connected to priority encoder 208. Quantized signals w1 232, w2 234, and w3 236 are received by priority encoder 208, which processes them to produce, at an output 238, a two-bit digital signal “y” comprising a least significant bit (LSB) signal “y1” 240 and a most significant bit (MSB) signal “y2” 242. FIG. 2B is a truth table 244 for priority encoder 208. In truth table 244, LOW and HIGH are encoded as, respectively, 0 and 1. When quantized signals w3 236, w2 234, and w1 232 are equal to, respectively, 0, 0, and 0, bit signals y2 242 and y1 240 are equal to, respectively, 0 and 0, which corresponds to binary number 0. When quantized signals w3 236, w2 234, and w1 232 are equal to, respectively, 0, 0, and 1, bit signals y2 242 and y1 240 are equal to, respectively, 0 and 1, which corresponds to binary number 1. When quantized signals w3 236, w2 234, and w1 232 are equal to, respectively, 0, 1, and 1, bit signals y2 242 and y1 240 are equal to, respectively, 1 and 0, which corresponds to binary number 2. When quantized signals w3 236, w2 234, and w1 232 are equal to, respectively, 1, 1, and 1, bit signals y2 242 and y1 240 are equal to, respectively, 1 and 1, which corresponds to binary number 3.
The skilled artisan will appreciate that, with additional comparators and resistors and by using a priority encoder capable of processing additional quantized signals, flash ADC 200 can be modified so that digital signal y comprises more than two bit signals. Alternatively, flash ADC 200 can be modified so that digital signal y comprises one bit signal.
Implementations of comparators A 202, B 204, and C 206 often use latch circuits, and are referred to as latch comparators. FIG. 3 is a schematic diagram of an exemplary conventional latch circuit 300 that can be used in an implementation of any of comparators A 202, B 204, or C 206. Latch circuit 300 comprises a bistable pair 302 connected between a reset switch 304 and analog ground VAG 218. (Alternatively, analog ground VAG 218 can be replaced by a first supply voltage “VSS”.) Preferably, bistable pair 302 comprises a first NMOSFET (n-channel Metal Oxide Semiconductor Field Effect Transistor) “M1” 306 and a second NMOSFET “M2” 308. Ideally, M1 306 and M2 308 are matched transistors. Preferably, each of M1 306 and M2 308 has a gain greater than one. However, bistable pair 302 can function if the product of the individual gains of M1 306 and M2 308 (i.e., the loop gain) is greater than one. The gate terminal of M2 308 is connected to the drain terminal of M1 306 at a first port “N4” 310. The gate terminal of M1 306 is connected to the drain terminal of M2 308 at a second port “N5” 312. The source terminals of M1 306 and M2 308 are together connected to analog ground VAG 218. In this configuration, M1 306 and M2 308 are said to be cross connected. Preferably, reset switch 304 comprises a third NMOSFET “M3” 314. The source terminal of M3 314 is connected to the drain terminal of one of M1 306 or M2 308; the drain terminal of M3 314 is connected the drain terminal of the other of M1 306 or M2 308. A clock waveform “Ck” 316 is applied to the gate terminal of M3 314. Ck 316 cycles between an “UP” voltage and an “DOWN” voltage at a sampling frequency.
The skilled artisan will appreciate that M1 306, M2 308, and M3 314 can also be realized in other field effect, junction, or combination transistor technologies. In general, reset switch 304 can be realized in a variety of switch technologies, including microelectromechanical embodiments. Latch circuit 300 can also be used for other applications.
For each latch circuit 300 in ADC 200, quantized signal “w” (e.g., w1 232, w2 234, or w3 236) is produced as an output voltage at N4 310 or N5 312. Latch circuit 300 is often preceded by an input stage (not shown) that includes a differential amplifier so that the voltage of analog signal x 228, applied at the noninverting terminal of the comparator, can be compared with the voltage at the inverting terminal of the comparator. For example, the voltage of analog signal x 228 is compared with V/4, for comparator A 202; V/2, for comparator B 204; and 3V/4, for comparator C 206.
The input stage produces a differential current signal comprising a first current signal “i1” 318 and a second current signal “i2” 320. First and second current signals i1 318 and i2 320 each comprise a bias current “ib” and a signal current “is”. The relationship between bias current ib and signal current is in first current signal i1 318 can be expressed as shown in Eq. (1):i1=ib+(½)(is),  Eq. (1)while the relationship between bias current ib and signal current is in second current signal i2 320 can be expressed as shown in Eq. (2):i2=ib−(½)(is).  Eq. (2)
The differential amplifier is configured so that first current signal i1 318 increases and decreases in response to, respectively, the rise and drop of the voltage of analog signal x 228, while second current signal i2 320 increases and decreases in response to, respectively, the drop and rise of the voltage of analog signal x 228. Thus, first and second current signals i1 318 and i2 320 always change currents in opposite directions, but the sum of first and second current signals i1 318 and i2 320 remains constant. In latch circuit 300, first current signal i1 318 and second current signal i2 320 are received as input current signals at, respectively, N4 310 and N5 312.
In latch circuit 300, when the voltage of Ck 316 is UP (i.e, the reset phase), M3 314 connects N4 310 with N5 312, so that the steady state voltages at both nodes are equal, and bias current ib flows through each of M1 306 and M2 308. Parasitic capacitances at each of nodes N4 310 and N5 312 are charged by bias current ib that flows through each of M1 306 and M2 308. The skilled artisan will appreciate that the parasitic capacitance at, for example, N4 310, includes the gate-to-source capacitance of M2 308, the drain-to-substrate capacitance of M1 306, the drain-to-substrate capacitance of M3 314, and the capacitance of the wiring connecting circuit devices. Bias current ib charges the parasitic capacitances at each of nodes N4 310 and N5 312 so that the voltages at N4 310 and N5 312 are at a “MID” value that is between LOW and HIGH. The gate and drain terminals of M1 306 and M2 308 are connected together. M1 306 and M2 308 are sized so that, under these conditions, they operate in “ON” states.
When the voltage of Ck 316 is DOWN (i.e., the sampling phase), the states of M1 306 and M2 308 are controlled by first and second current signals i1 318 and i2 320. For example, when first current signal i1 318 is greater than bias current ib and second current signal i2 320 is less than bias current ib, a transient is initiated to force M1 306 to operate in an “OFF” state, while M2 308 remains operating in an ON state. The course of this transient depends on how first and second current signals i1 318 and i2 320 change during the sampling phase. However, if M1 306 is turned OFF and the parasitic capacitances at N4 310 are fully charged by first current signal i1 318 (i.e., at a new steady state), the voltage at N4 310 is HIGH and the voltage at N5 312 is LOW. The transient can be explained in two parts. The first part describes the changes that occur while M1 306 remains ON. The second part depicts the conclusion of the excursion after M1 306 is turned OFF.
When first current signal i1 318 is greater than bias current ib, first current signal i1 318 continues to charge the parasitic capacitances at N4 310, which causes the voltage at N4 310 to rise. This is indicated by a small up-arrow “a” 322. Contemporaneously, when second current signal i2 320 is less than bias current ib, the parasitic capacitances at N5 312 start to discharge, which causes the voltage at N5 312 to drop. This is indicated by a small down-arrow “b” 324.
Because the voltage at N4 310 is also the voltage at the gate terminal of M2 308, the voltage at the gate terminal of M2 308 rises by the same amount as the rise in the voltage at N4 310. This is indicated by a small up-arrow “c” 326, where small up-arrow c 326 has the same length (i.e., the same change in voltage) as small up-arrow a 322. Because the voltage at the source terminal of M2 308 is held at analog ground VAG 218, the gate-to-source voltage of M2 308 increases by the same amount as the rise in the voltage at the gate terminal of M2 308. The increase in the gate-to-source voltage of M2 308 causes its drain current to increase. In response to the increase in the gate-to-source voltage of M2 308 and the increase in its drain current, the drain-to-source voltage of M2 308 decreases by a greater magnitude than the increase in its gate-to-source voltage. This is indicated by a large down-arrow “d” 328, where large down-arrow d 328 has a longer length (i.e., a larger change in voltage) than small up-arrow c 326. Because the voltage at the source terminal of M2 308 is held at analog ground VAG 218, the voltage at N5 312 drops by the same amount as the decrease in drain-to-source voltage of M2 308. Thus, the voltage at N5 312 drops under the relatively small effect of second current signal i2 320 being less than bias current ib (i.e., small down-arrow b324), and the relatively large effect of the decrease in the drain-to-source voltage of M2 308 (i.e., large down-arrow d 328).
Likewise, because the voltage at N5 312 is also the voltage at the gate terminal of M1 306, the voltage at the gate terminal of M1 306 drops by the same amount as the drop in the voltage at N5 312. This is indicated by a small down-arrow “e” 330, where small down-arrow e 330 has the same length (i.e., the same change in voltage) as small down-arrow b 324. Because the voltage at the source terminal of M1 306 is held at analog ground VAG 218, the gate-to-source voltage of M1 306 decreases by the same amount as the drop in the voltage at the gate terminal of M1 306. The decrease in the gate-to-source voltage of M1 306 causes its drain current to decrease. In response to the decrease in the gate-to-source voltage of M1 306 and the decrease in its drain current, the drain-to-source voltage of M1 306 increases by a greater magnitude than the decrease in its gate-to-source voltage. This is indicated by a large up-arrow “f” 332, where large up-arrow f 332 has a longer length (i.e., a larger change in voltage) than small down-arrow e 330. Because the voltage at the source terminal of M1 306 is held at analog ground VAG 218, the voltage at N4 310 rises by the same amount as the increase in drain-to-source voltage of M1 306. Thus, the voltage at N4 310 rises under the relatively small effect of first current signal i1 318 being greater than bias current ib (i.e., small up-arrow a 322) and the relatively large effect of the increase in the drain-to-source voltage of M1 306 (i.e., large up-arrow f 332).
The increasing of the drain-to-source voltage of M1 306 and the decreasing of the drain-to-source voltage of M2 308 reinforce each other. The gate-to-source voltage of M1 306 decreases with the drain-to-source voltage of M2 308 until M1 306 is turned OFF.
When M1 306 is OFF, it does not conduct current. Without drain current, the decreasing of the gate-to-source voltage of M1 306 no longer effects its drain-to-source voltage. Thus, the voltage at N4 310 continues to rise solely under the relatively small effect of first current signal i1 318 being greater than bias current ib (i.e., small up-arrow a 322) until the parasitic capacitances at N4 310 are fully charged and the voltage at N4 310 is HIGH.
However, because the voltage at N4 310 is also the voltage at the gate terminal of M2 308, the voltage at the gate terminal of M2 308 continues to rise. Because M2 308 remains ON, the increase in its gate-to-source voltage causes the drain current of M2 308 to increase, which in turn causes its drain-to-source voltage to decrease by a greater magnitude than the increase in the gate-to-source voltage of M2 308. Thus, the voltage at N5 312 continues to drop under the relatively small effect of second current signal i2 320 being less than bias current ib (i.e., small down-arrow b 324) and the relatively large effect of the decrease in the drain-to-source voltage of M2 308 (i.e., large down-arrow d 328) until the discharge of the parasitic capacitances at N5 312 is balanced and the voltage at N5 312 is LOW.
Therefore, it is a characteristic of latch circuit 300 that the port (i.e., N4 310 or N5 312) receiving the current signal (i.e., i1 318 or i2 320) that is greater than bias current ib requires more time to reach its new steady state voltage than the port receiving the current signal that is less than bias current ib. In practical implementations of latch circuit 300, the port receiving the current signal that is greater than bias current ib can require three to five times as much time to reach its new steady state voltage as that of the port receiving the current signal that is less than bias current ib. This limitation determines the frequency of Ck 316, and ultimately the processing speed of ADC 200.
Furthermore, if first and second current signals i1 318 and i2 320 both have values near to that of bias current ib (i.e., small signal current is), it is possible that the output voltage (at N4 310 or N5 312) may not reach LOW or HIGH before the end of the sampling phase. In this situation, ADC 200 does not produce a digital output. Such a “non-decision” is referred to as a “bit error”. Bit errors can adversely effect the performance of a system that uses the digital output of ADC 200. Such systems typically require bit error rates on an order of 10−18 to 10−16. Traditionally, bit errors are reduced by cascading latch comparators, where the overall bit error rate of the system is the product of the bit error rate of each cascaded latch comparator. However, this solution delays processing, complicates circuit design, uses additional die area, and consumes more power. Thus, there is a need to decrease the time necessary for the port (i.e., N4 310 or N5 312) receiving the current signal (i.e., i1 318 or i2 320) that is greater than bias current ib to reach its new steady state voltage.